Abstract: Fine grain reconfigurability carried out at the transistor level, i.e. the ability to switch between n- and p-type operation, offers new possibilities for highly efficient logic gates. In ...
Abstract: Designers primary goal is to develop the Adder cell with improved performance viz. speed, fixed rise and fall time, as it the fundamental block in VLSI design process. The dynamic logic ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback