EDN

Sequential logic equivalence checker claims huge speed boost

SAN FRANCISCO — Electronic system level (ESL) EDA startup Calypto Design Systems Inc. Monday (May 22) released version 2.0 of its SLEC sequential logic equivalence checking product family, claiming a ...
Electronic Design

Equivalence Checker Handles Sequential Logic

For electronic system-level (ESL) methodologies to come to fruition, designers need to be able to nimbly move between levels of abstraction, especially when it comes to sequential logic. Design is ...
Design-Reuse

Cadence Introduces the Conformal Smart Logic Equivalence Checker

SAN JOSE, Calif., Sept. 13, 2017 – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Conformal® Smart Logic Equivalence Checker (LEC), the next-generation equivalence checking ...
Design-Reuse

Pitfalls for Logical Equivalence Check

The VLSI design cycle is partitioned into two phases i.e. front-end and back-end phases of the complete SoC design cycle. While at front-end, most of the architectural specifications, coding and ...
Semiconductor Engineering

Leveraging Symbolic Simulations For IO Verification

IO libraries and interface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Interface IPs are the literal ...
Electronic Design

Sequential-Logic Equivalence Checker Gains Capacity And Speeds Up Runtimes

Checking functional equivalency between system-level models expressed in SystemC or C/C++ and their corresponding RTL representations is an important step toward making the high-level models useful in ...