Semiconductor Engineering

Robust Latch Hardened Against QNUs for Safety-Critical Applications in 22nm CMOS Technology

A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of ...
EDN

Susceptibility of an Application to ESD-Induced Latch-up

All semiconductor devices are sensitive to electrostatic discharge (ESD) damage to varying degrees. This is true whether they are soldered to a PC board in an application, or whether they are ...
Electronic Design

Automated and Context-Aware Latch-Up Checking

This white paper reviews how the increase in the number of power domains and voltages used in today's IC design has increased the importance of identifying and eliminating areas of susceptibility to ...
EDN

Single event upset and recovery

The effects of cosmic rays were once discussed in “Doubled-up MOSFETs“. The idea was that component redundancy, paired MOSFETs in that case, would allow one MOSFET to still function even if its ...
Electronic Design

It's A Jungle Up There: Radiation Effects In CMOS Devices

For a place we think of as the ultimate void, space is populated with many high-energy particles that can damage semiconductor devices. There are electrons and ...