Design-Reuse

Cutting a fast path to semiconductors: With special synthesis and processing, algorithms turn into silicon-but keep an eye on hardware

So you have an algorithm or a compute-intensive function you want to implement in hardware. Does that mean you have to go through the traditional ASIC design flow, writing register-transfer-level VHDL ...
Electronic Design

C Synthesis Nurtures FPGA Development

This Synthesis-Tool Package Gives The Designer An Inexpensive And Effective Method For Evaluating C-Based Methodologies. The design starts that use reconfigurable processors—namely field-programmable ...
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Customers will be able to transfer VHDL and Verilog ...
EDN

High-level synthesis rollouts enable ESL

SANTA CRUZ, Calif. — Three vendors promise to lift ASIC and FPGA designers above today's RTL design methodologies with high-level synthesis tools they will roll out this week. Though the companies all ...
Design-Reuse

Simplifying DSP Hardware Development within a MATLAB-based Design Flow

Historically, exploiting FPGA or ASIC implementation of DSP algorithms has been the domain of companies with highly-skilled designers and large budgets. Now, a new generation of tools is bringing ...